`include "defines.v"

// 将指令向译码模块传递
module if_id(

    input wire clk,
    input wire rst,
    input wire int_flag_i,//外部中断输入信号

    input wire[`InstBus] inst_i,            // 指令内容 `define InstBus 31:0
    input wire[`InstAddrBus] inst_addr_i,   // 指令地址 `define InstAddrBus 31:0

    input wire[`Hold_Flag_Bus] hold_flag_i, // 流水线暂停标志

    output reg[`InstBus] inst_o,            // 指令内容
    output reg[`InstAddrBus] inst_addr_o,    // 指令地址

    //to clint
    output reg int_flag_o
    );

    always @ (posedge clk) begin
        if (rst == `RstEnable) begin
            inst_o <= `INST_NOP;    //`define INST_NOP    32'h00000001
            inst_addr_o <= `ZeroWord;   //`define ZeroWord 32'h0
            int_flag_o <= `INT_NONE;
        // 流水线暂停时指令内容传递默认值
        end else if (hold_flag_i >= `Hold_If) begin     //define Hold_If   3'b010
            inst_o <= `INST_NOP;     //`define INST_NOP    32'h00000001
            inst_addr_o <= inst_addr_i;
            int_flag_o <=  `INT_NONE;
        end else begin
            inst_o <= inst_i;
            inst_addr_o <= inst_addr_i;
            int_flag_o <= int_flag_i;
        end
    end

endmodule